CB2016T2R2M [Linear Systems]
Dual Monolithic 300mA Synchronous Step-Down Regulaor; 双单片300毫安同步降压型Regulaor
| 型号： | CB2016T2R2M |
| 厂家： | 
Linear Systems |
| 描述： | Dual Monolithic 300mA Synchronous Step-Down Regulaor |
| 文件： | 总16页 (文件大小：278K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3547
Dual Monolithic
300mA Synchronous
Step-Down Regulator
U
DESCRIPTIO
FEATURES
The LTC®3547 is a dual, 2.25MHz, constant-frequency,
synchronous step-down DC/DC converter in a tiny 3mm
× 2mm DFN package. 100% duty cycle provides low drop-
out operation, extending battery life in portable systems.
Low output voltages are supported with the 0.6V feed-
back reference voltage. Each regulator can supply 300mA
continuous output current.
■
High Efficiency Dual Step-Down Outputs: Up to 96%
■
300mA Output Current per Channel at V = 3V
IN
■
■
Automatic Low Ripple Burst Mode Operation
(20mV )
P-P
Only 40µA Quiescent Current During Operation
(Both Channels)
■
■
■
■
■
■
2.25MHz Constant-Frequency Operation
2.5V to 5.5V Input Voltage Range
Low Dropout Operation: 100% Duty Cycle
Internally Compensated for All Ceramic Capacitors
Independent Internal Soft-Start for Each Channel
Current Mode Operation for Excellent Line and Load
Transient Response
The input voltage range is 2.5V to 5.5V, making it ideal for
Li-Ion and USB powered applications. Supply current dur-
ingoperationisonly40µAanddropsto<1µAinshutdown.
Automatic Burst Mode® operation increases efficiency at
light loads, further extending battery life.
■
■
■
■
An internally set 2.25MHz switching frequency allows
the use of tiny surface mount inductors and capacitors.
Internal soft-start reduces inrush current during start-
up. All outputs are internally compensated to work with
ceramic capacitors. The LTC3547 is available in a low
profile(0.75mm)3mm×2mmDFNpackage.TheLTC3547
is also available in a fixed output voltage configuration,
eliminating the need for the external feedback networks
(see Table 2).
0.6V Reference Allows Low Output Voltages
Short-Circuit Protected
Ultralow Shutdown Current: I < 1µA
Q
Low Profile (0.75mm) 8-Lead 3mm × 2mm
DFN Package
U
APPLICATIO S
■
Cellular Telephones
■
Digital Still Cameras
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents,
including 6580258, 5481178, 6304066, 6127815, 6498466, 6611131.
■
Wireless and DSL Modems
■
PDAs/Palmtop PCs
■
Portable Media Players
U
Efficiency vs Output Current
TYPICAL APPLICATIO
for V
= 2.5V
OUT
100
90
80
70
60
50
40
30
20
10
0
1
Dual Monolithic Buck Regulator in 8-Lead 3mm × 2mm DFN
V
IN
2.5V TO 5.5V
0.1
4.7µF
RUN2
V
RUN1
IN
L2
4.7µH
L1
4.7µH
LTC3547
SW2
SW1
0.01
0.001
0.0001
V
V
OUT1
OUT2
2.5V AT
300mA
1.8V AT
300mA
10pF
475k
10pF
V
V
V
= 2.7V
= 3.6V
= 4.2V
IN
IN
IN
V
FB2
V
FB1
GND
475k
4.7µF
4.7µF
237k
150k
0.1
1
10
100
1000
3547 TA01
OUTPUT CURRENT (mA)
3547 TA01b
3547fa
1
LTC3547
W W U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
V ............................................................... –0.3V to 6V
IN
V
, V ......................................... –0.3V to V +0.3V
FB1 FB2
IN
IN
IN
V
1
2
3
4
8
7
6
5
V
FB2
FB1
RUN1, RUN2..................................... –0.3V to V +0.3V
SW1, SW2 (DC)................................ –0.3V to V +0.3V
RUN1
RUN2
SW2
GND
9
V
IN
SW1
P-Channel Switch Source Current (DC) ...............500mA
N-Channel Switch Sink Current (DC) ...................500mA
Peak SW Sink and Source Current (Note 5).........700mA
Ambient Operating Temperature Range ... –40°C to 85°C
Maximum Junction Temperature .......................... 125°C
Storage Temperature Range................... –65°C to 125°C
DDB PACKAGE
8-LEAD (3mm × 2mm) PLASTIC DFN
= 125°C, θ = 76°C/W
T
JMAX
JA
EXPOSED PAD (PIN 9) IS GND MUST BE SOLDERED TO PCB
ORDER PART NUMBER
DDB PART MARKING
LTC3547EDDB
LTC3547EDDB-1
LCDP
LCPC
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 3.6V, unless otherwise noted.
A
IN
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
5.5
UNITS
●
●
V
V
Operating Voltage
2.5
V
V
IN
IN
IN
V
UV
V
Undervoltage Lockout
V
IN
Low to High
2.0
3
2.5
●
●
I
Feedback Pin Input Current
LTC3547, V = V
FBREG
30
6
nA
µA
FB
FB
LTC3547-1, V = V
FB
FBREG
V
Regulated Feedback Voltage (V
)
)
LTC3547, 0°C ≤ T ≤ 85°C
0.590
0.588
1.770
1.764
0.600
0.600
1.800
1.800
0.610
0.612
1.830
1.836
V
V
V
V
FBREG1
FBREG2
FB1
A
●
●
LTC3547, –40°C ≤ T ≤ 85°C
A
LTC3547-1, 0°C ≤ T ≤ 85°C
A
LTC3547-1, –40°C ≤ T ≤ 85°C
A
V
Regulated Feedback Voltage (V
LTC3547, 0°C ≤ T ≤ 85°C
0.590
0.588
1.180
1.176
0.600
0.600
1.200
1.200
0.610
0.612
1.220
1.224
V
V
V
V
FB2
A
●
●
LTC3547, –40°C ≤ T ≤ 85°C
A
LTC3547-1, 0°C ≤ T ≤ 85°C
A
LTC3547-1, –40°C ≤ T ≤ 85°C
A
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
= 2.5V to 5.5V
0.3
0.5
0.5
%/V
%
IN
Δ
Δ
V
V
LINEREG
I
= 0mA to 300mA
LOAD
LOADREG
I
Input DC Supply Current
Active Mode (Note 3)
Sleep Mode
S
V
V
= V = 0.95V × V
FBREG
450
40
0.1
700
60
1
µA
µA
µA
FB1
FB1
FB2
= V = 1.05V × V
, V = 5.5V
FB2
FBREG IN
Shutdown
RUN1 = RUN2 = 0V, V = 5.5V
IN
●
f
I
Oscillator Frequency
V
= 0.6V
1.8
2.25
2.7
MHz
OSC
FB
IN
Peak Switch Current Limit
Channel 1 (300mA)
Channel 2 (300mA)
V
= 3V, V < V
, Duty Cycle < 35%
LIM
FB
FBREG
mA
mA
400
400
550
550
3547fa
2
LTC3547
ELECTRICAL CHARACTERISTICS The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 3.6V, unless otherwise noted.
A
CC
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
R
Channel 1 (Note 4)
DS(ON)
Top Switch On-Resistance
Bottom Switch On-Resistance
Channel 2 (Note 4)
V
V
= 3.6V, I = 100mA
0.8
1.05
1.05
Ω
Ω
IN
IN
SW
= 3.6V, I = 100mA
0.75
SW
Top Switch On-Resistance
Bottom Switch On-Resistance
V
V
= 3.6V, I = 100mA
0.8
0.75
1.05
1.05
Ω
Ω
IN
IN
SW
= 3.6V, I = 100mA
SW
I
t
Switch Leakage Current
Soft-Start Time
V
= 5V, V = 0V
RUN
0.01
0.650
1
1
0.850
1.2
1
µA
ms
V
SW(LKG)
IN
V
FB
From 10% to 90% Full-Scale
0.450
0.4
SOFTSTART
●
●
V
RUN Threshold High
RUN Leakage Current
RUN
RUN
I
0.01
20
µA
V
Output Ripple in Burst Mode Operation
V
OUT
= 1.5V, C
= 4.7µF
mV
P-P
BURST
OUT
Note 4: The DFN switch on-resistance is guaranteed by correlation to
wafer level measurements.
Note 5: Guaranteed by long term current density limitations.
Note 6: This IC includes overtemperature protection that is intended
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3547E is guaranteed to meet specified performance
from 0°C to 85°C. Specifications over the –40°C and 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Burst Mode Operation
Efficiency vs Input Voltage
Supply Current vs Temperature
60
55
50
45
40
35
30
25
20
100
90
80
70
60
50
40
30
RUN1 = RUN2 = V
IN
LOAD
V
= 1.8V
OUT
SW, AC
COUPLED
5V/DIV
I
= 0A
V
OUT
50mV/DIV
V
= 5.5V
= 2.7V
IN
I
L
50mA/DIV
I
I
I
I
I
= 0.1mA
OUT
OUT
OUT
OUT
OUT
V
IN
= 1mA
3547 G01
= 10mA
= 100mA
= 300mA
2.5µs/DIV
V
V
LOAD
= 3.6V
IN
= 1.8V
OUT
I
= 20mA
50
100
4.5
(V)
5.5
–50 –25
0
25
75
2.5
3
3.5
4
5
TEMPERATURE (ºC)
V
IN
3547 G03
3547 G02
3547fa
3
LTC3547
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Oscillator Frequency
vs Temperature
Switch Leakage vs Temperature
Switch Leakage vs Input Voltage
500
400
300
200
100
0
2.6
50
40
30
20
10
0
2.5
2.4
V
= 4.2V
IN
2.3
2.2
2.1
2.0
1.9
V
V
= 3.6V
= 2.7V
IN
IN
SYNCHRONOUS
SWITCH
SYNCHRONOUS
SWITCH
MAIN SWITCH
MAIN SWITCH
1.8
3
3.5
4.5
(V)
5
5.5
6
2.5
4
–25
0
50
75 100 125
–25
0
50
75 100 125
–50
25
–50
25
V
TEMPERATURE (°C)
TEMPERATURE (°C)
IN
3547 G06
3547 G04
3547 G05
Reference Voltage
vs Temperature
R
vs Input Voltage
R
vs Temperature
DS(ON)
DS(ON)
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
612
608
1.0
0.9
0.8
0.7
0.6
0.5
0.4
V
= 2.7V
IN
MAIN SWITCH
V
= 3.6V
IN
604
600
596
SYNCHRONOUS
SWITCH
MAIN SWITCH
SYNCHRONOUS
SWITCH
592
588
V
= 4.2V
IN
–25
0
50
75 100 125
–25
0
50
75
100
–50
25
–50
25
3
3.5
4.5
(V)
5
5.5
6
2.5
4
TEMPERATURE (°C)
TEMPERATURE (°C)
V
IN
3547 G09
3547 G07
3547 G08
Efficiency vs Load Current
Efficiency vs Load Current
Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
OUT
= 2.5V
V
= 1.2V
V
= 1.8V
OUT
OUT
V
V
V
= 2.7V
= 3.6V
= 4.2V
V
V
V
= 2.7V
= 3.6V
= 4.2V
V
V
V
= 2.7V
= 3.6V
= 4.2V
IN
IN
IN
IN
IN
IN
IN
IN
IN
0.1
1
10
100
1000
0.1
1
10
100
1000
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
3547 G12
3547 G10
3547 G11
3547fa
4
LTC3547
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Load Regulation
Line Regulation
0.6
0.4
1.2
1.O
0.8
0.6
0.4
0.2
0
V
I
= 1.8V
V
V
V
= 1.2V
= 1.8V
= 2.5V
V
= 3.6V
IN
OUT
LOAD
OUT
OUT
OUT
= 100mA
0.2
0
Burst Mode
OPERATION
–0.2
–0.4
–0.6
–0.2
3
3.5
4.5
5
5.5
2.5
4
50
100
200 250 300 350
0
150
V
(V)
LOAD CURRENT (mA)
IN
3547 G14
3547 G13
Start-Up From Shutdown
Start-Up From Shutdown
Load Step
V
, AC
OUT
RUN
2V/DIV
RUN
2V/DIV
COUPLED
100mV/DIV
V
V
OUT
OUT
1V/DIV
1V/DIV
I
L
200mA/DIV
I
I
LOAD
I
L
L
200mA/DIV
100mA/DIV
200mA/DIV
3547 G17
3547 G15
3547 G16
10µs/DIV
250µs/DIV
200µs/DIV
V
V
I
= 3.6V
OUT
LOAD
V
V
I
= 3.6V
V
V
I
= 3.6V
IN
IN
IN
= 1.8V
= 1.8V
= 0A
= 1.8V
OUT
LOAD
OUT
= 0mA TO 300mA
= 300mA
LOAD
Load Step
Load Step
V
, AC
V
, AC
OUT
OUT
COUPLED
COUPLED
100mV/DIV
100mV/DIV
I
I
L
L
200mA/DIV
200mA/DIV
I
I
LOAD
200mA/DIV
LOAD
200mA/DIV
3547 G18
3547 G19
10µs/DIV
= 20mA TO 300mA
10µs/DIV
= 50mA TO 300mA
V
V
LOAD
= 3.6V
OUT
V
V
= 3.6V
IN
OUT
I
LOAD
IN
= 1.8V
= 1.8V
I
3547fa
5
LTC3547
U
U
U
PI FU CTIO S
V
(Pin 1): Regulator 1 Output Feedback. Receives
SW2 (Pin 6): Regulator 2 Switch Node Connection to
FB1
the feedback voltage from the external resistor divider
across the regulator 1 output. Nominal voltage for this
pin is 0.6V.
the Inductor. This pin swings from V to GND.
IN
RUN2 (Pin 7): Regulator 2 Enable. Forcing this pin to
V
enables regulator 2, while forcing it to GND causes
IN
RUN1 (Pin 2): Regulator 1 Enable. Forcing this pin to
regulator 2 to shut down.
V
enables regulator 1, while forcing it to GND causes
IN
V
FB2
(Pin 8): Regulator 2 Output Feedback. Receives
regulator 1 to shut down.
the feedback voltage from the external resistor divider
across the regulator 2 output. Nominal voltage for this
pin is 0.6V.
V (Pin 3): Main Power Supply. Must be closely decou-
IN
pled to GND.
SW1 (Pin 4): Regulator 1 Switch Node Connection to the
Exposed Pad (Pin 9): Electrically Connected to GND.
Must be soldered to the PCB for optimum thermal
performance.
Inductor. This pin swings from V to GND.
IN
GND (Pin 5): Ground. Connect to the (–) terminal of C
,
OUT
and the (–) terminal of C .
IN
FUNCTIONAL DIAGRAM
REGULATOR 1
BURST
CLAMP
3
V
IN
SLOPE
COMP
–
V
FB1
1
–
+
SLEEP
–
+
I
TH
5Ω
EA
I
COMP
V
+
SLEEP
BURST
Q
0.6V
S
R
RS
LATCH
SOFT-START
Q
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
ANTI
SHOOT-
THRU
4
5
SW1
GND
+
–
I
RCMP
SHUTDOWN
2
7
SLEEP2
SLEEP1
RUN1
RUN2
0.6V REF
OSC
OSC
REGULATOR 2 (IDENTICAL TO REGULATOR 1)
8
6
SW2
V
FB2
3547 FD
3547fa
6
LTC3547
U
OPERATIO
The LTC3547 uses a constant-frequency current mode
architecture. The operating frequency is set at 2.25MHz.
Both channels share the same clock and run in-phase.
(Refer to Functional Diagram )
Dropout Operation
When the input supply voltage decreases toward the out-
put voltage the duty cycle increases to 100%, which is the
dropout condition. In dropout, the PMOS switch is turned
on continuously with the output voltage being equal to the
input voltage minus the voltage drops across the internal
P-channel MOSFET and the inductor.
The output voltage is set by an external resistor divider
returned to the V pins. An error amplifier compares the
FB
dividedoutputvoltagewithareferencevoltageof0.6Vand
regulates the peak inductor current accordingly.
An important design consideration is that the R
DS(ON)
Main Control Loop
of the P-channel switch increases with decreasing input
supply voltage (see Typical Performance Characteristics).
Therefore, theusershouldcalculatetheworst-casepower
dissipation when the LTC3547 is used at 100% duty cycle
with low input voltage (see Thermal Considerations in the
Applications Information Section).
Duringnormaloperation,thetoppowerswitch(P-channel
MOSFET) is turned on at the beginning of a clock cycle
when the V voltage is below the reference voltage. The
FB
current into the inductor and the load increases until the
peak inductor current (controlled by I ) is reached. The
TH
RS latch turns off the synchronous switch and energy
stored in the inductor is discharged through the bottom
switch (N-channel MOSFET) into the load until the next
clock cycle begins, or until the inductor current begins to
Soft-Start
In order to minimize the inrush current on the input by-
pass capacitor, the LTC3547 slowly ramps up the output
voltage during start-up. Whenever the RUN1 or RUN2 pin
is pulled high, the corresponding output will ramp from
zero to full-scale over a time period of approximately
650µs. This prevents the LTC3547 from having to quickly
charge the output capacitor and thus supplying an exces-
sive amount of instantaneous current.
reverse (sensed by the I
comparator).
RCMP
The peak inductor current is controlled by the internally
compensated I voltage, which is the output of the er-
TH
ror amplifier. This amplifier regulates the V pin to the
FB
internal 0.6V reference by adjusting the peak inductor
current accordingly.
Burst Mode Operation
Short-Circuit Protection
Tooptimizeefficiency,theLTC3547automaticallyswitches
from continuous operation to Burst Mode operation when
the load current is relatively light. During Burst Mode op-
When either regulator output is shorted to ground, the
corresponding internal N-channel switch is forced on for
a longer time period for each cycle in order to allow the
inductor to discharge, thus preventing current runaway.
This technique has the effect of decreasing switching
frequency. Once the short is removed, normal operation
resumesandtheregulatoroutputwillreturntoitsnominal
voltage.
eration, the peak inductor current (as set by I ) remains
TH
fixedatapproximately60mAandthePMOSswitchoperates
intermittently based on load demand. By running cycles
periodically, the switching losses are minimized.
The duration of each burst event can range from a few
cycles at light load to almost continuous cycling with
short sleep intervals at moderate loads. During the sleep
intervals, the load current is being supplied solely from
the output capacitor. As the output voltage droops, the
error amplifier output rises above the sleep threshold,
signaling the burst comparator to trip and turn the top
MOSFET on. This cycle repeats at a rate that is dependent
on load demand.
3547fa
7
LTC3547
U
W U U
APPLICATIO S I FOR ATIO
A general LTC3547 application circuit is shown in
Figure 1. External component selection is driven by the
load requirement, and begins with the selection of the
Inductor Core Selection
Different core materials and shapes will change the
size/current and price/current relationship of an induc-
tor. Toroid or shielded pot cores in ferrite or permalloy
materials are small and do not radiate much energy, but
generally cost more than powdered iron core inductors
with similar electrical characteristics. The choice of which
style inductor to use often depends more on the price vs
sizerequirements,andanyradiatedfield/EMIrequirements,
than on what the LTC3547 requires to operate. Table 1
shows some typical surface mount inductors that work
well in LTC3547 applications.
inductor L. Once the inductor is chosen, C and C
IN
OUT
can be selected.
Inductor Selection
Although the inductor does not influence the operat-
ing frequency, the inductor value has a direct effect on
ripple current. The inductor ripple current ΔI decreases
L
with higher inductance and increases with higher V
IN
or V
:
OUT
⎛
⎞
⎟
⎠
VOUT
fO •L
VOUT
∆IL =
• 1−
Table 1. Representative Surface Mount Inductors
⎜
⎝
V
IN
MANU-
MAX DC
(1)
FACTURER PART NUMBER VALUE CURRENT DCR HEIGHT
Accepting larger values of ΔI allows the use of low
L
Taiyo Yuden CB2016T2R2M
CB2012T2R2M
2.2µH
2.2µH
3.3µH
510mA
530mA
410mA
0.13Ω 1.6mm
0.33Ω 1.25mm
0.27Ω 1.6mm
inductances, but results in higher output voltage ripple,
greater core losses, and lower output current capability.
A reasonable starting point for setting ripple current
is 40% of the maximum output load current. So, for a
CB2016T3R3M
Panasonic
Sumida
Murata
ELT5KT4R7M
CDRH2D18/LD
4.7µH
4.7µH
950mA
0.2Ω
1.2mm
630mA 0.086Ω 2mm
LQH32CN4R7M23 4.7µH
450mA
0.2Ω
2mm
300mA regulator, ΔI = 120mA (40% of 300mA).
L
Taiyo Yuden NR30102R2M
NR30104R7M
2.2µH 1100mA
4.7µH
0.1Ω
0.19Ω
1mm
1mm
The inductor value will also have an effect on Burst Mode
operation. The transition to low current operation begins
when the peak inductor current falls below a level set by
the internal burst clamp. Lower inductor values result in
higher ripple current which causes the transition to occur
at lower load currents. This causes a dip in efficiency in
the upper range of low current operation. Furthermore,
lower inductance values will cause the bursts to occur
with increased frequency.
750mA
FDK
FDKMIPF2520D
FDKMIPF2520D
FDKMIPF2520D
4.7µH 1100mA 0.11Ω
3.3µH 1200mA 0.1Ω
2.2µH 1300mA 0.08Ω
1mm
1mm
1mm
TDK
VLF3010AT4R7- 4.7µH
MR70
700mA
0.24Ω
1mm
1mm
1mm
VLF3010AT3R3- 3.3µH
MR87
870mA
0.17Ω
VLF3010AT2R2- 2.2µH 1000mA 0.12Ω
M1RD
V
IN
2.5V TO 5.5V
C1
RUN2
V
IN
RUN1
LTC3547
SW2
SW1
L2
L1
V
OUT2
V
OUT1
C
C
F1
F2
V
V
FB1
FB2
GND
R4
R2
C
C
OUT1
OUT2
R3
R1
3547 F01
Figure 1. LTC3547 General Schematic
3547fa
8
LTC3547
U
W U U
APPLICATIO S I FOR ATIO
Input Capacitor (C ) Selection
where f = operating frequency, C
= output capacitance
IN
OUT
and ΔI = ripple current in the inductor. For a fixed output
L
In continuous mode, the input current of the converter
is a square wave with a duty cycle of approximately
voltage, the output ripple is highest at maximum input
voltage since ΔI increases with input voltage.
L
V
/V . To prevent large voltage transients, a low equiv-
OUT IN
alent series resistance (ESR) input capacitor sized for
the maximum RMS current must be used. The max-
imum RMS capacitor current is given by:
Iftantalumcapacitorsareused,itiscriticalthatthecapaci-
tors are surge tested for use in switching power supplies.
AnexcellentchoiceistheAVXTPSseriesofsurfacemount
tantalum.Thesearespeciallyconstructedandtestedforlow
ESR so they give the lowest ESR for a given volume. Other
capacitor types include Sanyo POSCAP, Kemet T510 and
T495 series, and Sprague 593D and 595D series. Consult
the manufacturer for other specific recommendations.
VOUT(V − VOUT
)
IN
IRMS ≈ IMAX
(2)
V
IN
Where the maximum average output current I
equals
MAX
the peak current minus half the peak-to-peak ripple cur-
Using Ceramic Input and Output Capacitors
rent, I
= I – ΔI /2.
MAX
LIM L
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high
ripple current, high voltage rating and low ESR make
them ideal for switching regulator applications. Because
the LTC3547 control loop does not depend on the output
capacitor’s ESR for stable operation, ceramic capacitors
can be used freely to achieve very low output ripple and
small circuit size.
This formula has a maximum at V = 2V , where I
RMS
IN
OUT
= I /2. This simple worst-case is commonly used to
OUT
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple cur-
rent ratings are often based on only 2000 hours lifetime.
This makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required.Severalcapacitorsmayalsobeparalleledtomeet
the size or height requirements of the design. An addi-
tional0.1µFto1µFceramiccapacitorisalsorecommended
However, care must be taken when ceramic capacitors are
used at the input. When a ceramic capacitor is used at the
input and the power is supplied by a wall adapter through
long wires, a load step at the output can induce ringing at
on V for high frequency decoupling when not using an
IN
all-ceramic capacitor solution.
theinput, V . Atbest, thisringingcancoupletotheoutput
IN
and be mistaken as loop instability. At worst, a sudden
Output Capacitor (C ) Selection
OUT
inrush of current through the long wires can potentially
The selection of C
is driven by the required effective
OUT
cause a voltage spike at V , large enough to damage the
IN
series resistance (ESR). Typically, once the ESR require-
ment for C has been met, the RMS current rating
part. For more information, see Application Note 88.
OUT
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
generally far exceeds the I
output ripple ΔV
requirement. The
RIPPLE(P-P)
is determined by:
OUT
⎛
⎜
⎝
⎞
⎠
1
∆VOUT ≅ ∆IL ESR +
⎟
8fCOUT
(3)
3547fa
9
LTC3547
U
W U U
APPLICATIO S I FOR ATIO
Setting the Output Voltage
a load step occurs, V
immediately shifts by an amount
OUT
equal to ΔI
• ESR, where ESR is the effective series
LOAD
The LTC3547 regulates the V
and V
pins to 0.6V
FB1
FB2
resistance of C . ΔI
also begins to charge or dis-
OUT
LOAD
during regulation. Thus, the output voltage is set by a
chargeC generatingafeedbackerrorsignalusedbythe
OUT
resistive divider according to the following formula:
regulator to return V
this recovery time, V
to its steady-state value. During
can be monitored for overshoot
OUT
OUT
R2
R1
⎛
⎞
VOUT = 0.6V 1+
⎜
⎝
⎟
⎠
or ringing that would indicate a stability problem.
(4)
The initial output voltage step may not be within the band-
width of the feedback loop, so the standard second-order
overshoot/DCratiocannotbeusedtodeterminethephase
Keeping the current small (<5µA) in these resistors maxi-
mizes efficiency, but making it too small may allow stray
capacitance to cause noise problems or reduce the phase
margin of the error amp loop.
margin. In addition, feedback capacitors (C and C )
F1
F2
can be added to improve the high frequency response, as
To improve the frequency response of the main control
shown in Figure 1. Capacitor C provides phase lead by
F
loop, a feedback capacitor (C ) may also be used. Great
F
creating a high frequency zero with R2 which improves
care should be taken to route the V line away from noise
FB
the phase margin.
sources, such as the inductor or the SW line.
Theoutputvoltagesettlingbehaviorisrelatedtothestability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a re-
view of control loop theory, refer to Application Note 76.
Fixed output versions of the LTC3547 (e.g. LTC3547-1)
include an internal resistive divider, eliminating the need
for external resistors. The resistor divider is chosen such
that the V input current is 3µA. For these versions the
FB
V pin should be connected directly to V . Table 2 lists
FB
OUT
In some applications, a more severe transient can be
caused by switching in loads with large (>1µF) input ca-
pacitors. The discharged input capacitors are effectively
the fixed output voltages available for the LTC35476-1.
Table 2. Fixed Output Voltage Versions
PART NUMBER
LTC3547
V
V
OUT2
OUT1
put in parallel with C , causing a rapid drop in V
.
OUT
OUT
Adjustable
1.8V
Adjustable
1.2V
No regulator can deliver enough current to prevent this
problemiftheswitchconnectingtheloadhaslowresistance
and is driven quickly. The solution is to limit the turn-on
LTC3547-1
Checking Transient Response
™
speed of the load switch driver. A Hot Swap controller
is designed specifically for this purpose and usually in-
corporates current limiting, short-circuit protection, and
soft-starting.
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
Hot Swap is a trademark of Linear Technology Corporation.
3547fa
10
LTC3547
U
W U U
APPLICATIO S I FOR ATIO
Efficiency Considerations
bottom MOSFET switches. The gate charge losses are
proportional to V and thus their effects will be more
IN
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
pronounced at higher supply voltages.
2
3) I R losses are calculated from the DC resistances of
the internal switches, R , and external inductor,
SW
R . In continuous mode, the average output current
L
flows through inductor L, but is “chopped” between
the internal top and bottom switches. Thus, the series
resistance looking into the SW pin is a function of both
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
age of input power.
top and bottom MOSFET R
(DC) as follows:
and the duty cycle
DS(ON)
Although all dissipative elements in the circuit produce
losses, four sources usually account for the losses in
R
= (R
) • (DC) + (R
) • (1– DC)
(5)
SW
DS(ON)TOP
DS(ON)BOT
LTC3547 circuits: 1) V quiescent current, 2) switching
IN
2
The R
for both the top and bottom MOSFETs can
losses, 3) I R losses, 4) other system losses.
DS(ON)
be obtained from the Typical Performance Character-
1) The V current is the DC supply current given in the
2
IN
istics curves. Thus, to obtain I R losses:
Electrical Characteristics which excludes MOSFET
2
2
I R losses = I
• (R + R )
SW L
driver and control currents. V current results in a
OUT
IN
small (<0.1%) loss that increases with V , even at
IN
4) Other “hidden” losses, such as copper trace and in-
ternal battery resistances, can account for additional
efficiency degradations in portable systems. It is very
important to include these “system” level losses in
the design of a system. The internal battery and fuse
resistancelossescanbeminimizedbymakingsurethat
no load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current re-
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
C has adequate charge storage and very low ESR at
IN
the switching frequency. Other losses, including diode
conduction losses during dead-time, and inductor
core losses, generally account for less than 2% total
additional loss.
from V to ground. The resulting dQ/dt is a current out
IN
of V that is typically much larger than the DC bias cur-
IN
rent.Incontinuousmode,I
Q and Q are the gate charges of the internal top and
=f (Q +Q ),where
GATECHG
O T B
T
B
3547fa
11
LTC3547
U
W U U
APPLICATIO S I FOR ATIO
Thermal Considerations
PC Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3547. These items are also illustrated graphically
in the layout diagrams of Figures 2 and 3. Check the fol-
lowing in your layout:
In a majority of applications, the LTC3547 does not dis-
sipate much heat due to its high efficiency. In the unlikely
event that the junction temperature somehow reaches
approximately 150°C, both power switches will be turned
off and the SW node will become high impedance.
1. Does the capacitor C connect to the power V (Pin 3)
The goal of the following thermal analysis is to determine
whetherthepowerdissipatedcausesenoughtemperature
risetoexceedthemaximumjunctiontemperature(125°C)
of the part. The temperature rise is given by:
IN
IN
and GND (Pin 5) as closely as possible? This capacitor
provides the AC current of the internal power MOSFETs
and their drivers.
2. Are the respective C
and L closely connected?
OUT
T
= P • θ
(6)
RISE
D
JA
The (–) plate of C
returns current to GND and the
OUT
Where P is the power dissipated by the regulator and
JA
to the ambient temperature.
D
(–) plate of C .
IN
θ
is the thermal resistance from the junction of the die
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C and a ground sense
OUT1
The junction temperature, T , is given by:
J
line terminated near GND (Pin 5). The feedback sig-
nals V and V should be routed away from noisy
T = T
+ T
AMBIENT
(7)
FB1
FB2
J
RISE
components and traces, such as the SW lines (Pins 4
and 6), and their trace length should be minimized.
As a worst-case example, consider the case when the
LTC3547 is in dropout on both channels at an input volt-
age of 2.7V with a load current of 300mA and an ambi-
ent temperature of 70°C. From the Typical Performance
4. Keep sensitive components away from the SW pins if
possible. The input capacitor C and the resistors R1,
IN
R2, R3 and R4 should be routed away from the SW
Characteristics graph of Switch Resistance, the R
DS(ON)
traces and the inductors.
of the main switch is 0.9Ω. Therefore, power dissipated
by each channel is:
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GND pin at a single
point. These ground traces should not share the high
2
P = I
• R
= 81mV
DS(ON)
D
OUT
Given that the thermal resistance of a properly soldered
DFN package is approximately 76°C/W, the junction
temperature of an LTC3547 device operating in a 70°C
ambient temperature is approximately:
current path of C or C
.
IN
OUT
6. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power components. These copper areas should be
T = (2 • 0.081W • 76°C/W) + 70°C = 82.3°C
J
which is well below the absolute maximum junction tem-
perature of 125°C.
connected to V or GND.
IN
3547fa
12
LTC3547
U
W U U
APPLICATIO S I FOR ATIO
V
IN
2.5V TO 5.5V
C1
RUN2
V
IN
RUN1
LTC3547
SW2
SW1
L2
L1
V
V
OUT1
OUT2
C
F2
C
F1
V
V
FB1
FB2
GND
R4
R2
C
C
OUT1
OUT2
R3
R1
3547 F02
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 2. LTC3547 Layout Diagram (See Board Layout Checklist)
R1
R2
R3
R4
VIA TO GND
VIA TO GND
VIA TO V
V
V
FB2
FB1
VIA TO V
OUT1
OUT2
C
F2
C
F2
VIA TO V
IN
V
IN
SW2
L2
C
IN
SW1
L1
GND
V
OUT2
C
OUT2
C
OUT1
3547 F03
V
OUT1
Figure 3. LTC3547 Suggested Layout
3547fa
13
LTC3547
U
W U U
APPLICATIO S I FOR ATIO
Design Example
The feedback resistors program the output voltage. To
maintain high efficiency at light loads, the current in these
resistors should be kept small. Choosing 2µA with the
0.6V feedback voltage makes R1~300k. A close standard
1% resistor is 280k. Using Equation 4:
As a design example, consider using the LTC3547 in a
portable application with a Li-Ion battery. The battery
provides a V ranging from 2.8V to 4.2V. The load on
IN
each channel requires a maximum of 300mA in active
mode and 2mA in standby mode. The output voltages are
V
⎛
⎞
OUT
R2 =
− 1 •R1= 887k
⎜
⎝
⎟
⎠
V
OUT1
= 2.5V and V
= 1.8V.
OUT2
0.6
Start with channel 1. First, calculate the inductor value
for about 40% ripple current (120mA in this example) at
An optional 10pF feedback capacity (C ) may be used to
F1
improve transient response.
maximum V . Using a derivation of Equation 1:
IN
Using the same analysis for channel 2 (V
the results are:
= 1.8V),
OUT2
2.5V
2.5V
4.2V
⎛
⎞
L1=
• 1−
= 3.75µH
⎜
⎝
⎟
⎠
2.25MHz •(120mA)
L2 = 3.81µH
R3 = 280k
R4 = 560k
For the inductor, use the closest standard value of 4.7µH.
A 4.7µF capacitor should be more than sufficient for this
output capacitor. As for the input capacitor, a typical value
of C = 4.7µF should suffice, as the source impedance of
a Li-Ion battery is very low.
Figure 4 shows the complete schematic for this example,
along with the efficiency curve and transient response.
IN
V
IN
2.5V TO 5.5V
C1
4.7µF
RUN2
V
RUN1
IN
L2
4.7µH
L1
4.7µH
LTC3547
SW2
SW1
V
V
OUT1
OUT2
1.8V AT 300mA
2.5V AT 300mA
C
, 10pF
C
, 10pF
R2
F2
F1
V
V
FB1
FB2
GND
R4
562k
R3
280k
R1
C
C
OUT2
4.7µF
OUT1
4.7µF
280k 887k
3547 F04a
C1, C2, C3: TAIYO YUDEN JMK316BJ475ML
L1, L2: MURATA LQH32CN4R7M33
Figure 4a. Design Example Circuit
100
100
V
OUT
= 2.5V
V
= 1.8V
OUT
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
V
V
V
= 2.7V
= 3.6V
= 4.2V
V
V
V
= 2.7V
= 3.6V
= 4.2V
IN
IN
IN
IN
IN
IN
0.1
1
10
100
1000
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
3547 F04b
Figure 4b. Efficiency vs Output Current
3547fa
14
LTC3547
U
W U U
APPLICATIO S I FOR ATIO
V
, AC
V
, AC
OUT
OUT
COUPLED
COUPLED
100mV/DIV
100mV/DIV
I
I
L
L
200mA/DIV
200mA/DIV
I
I
LOAD
200mA/DIV
LOAD
200mA/DIV
3547 F04c
10µs/DIV
= 20mA TO 300mA
10µs/DIV
= 20mA TO 300mA
V
V
LOAD
= 3.6V
OUT
V
V
= 3.6V
IN
OUT
I
LOAD
IN
= 1.8V
= 2.5V
I
Figure 4c. Transient Response
U
PACKAGE DESCRIPTIO
DDB Package
8-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1702 Rev B)
0.61 0.05
(2 SIDES)
R = 0.115
0.40 0.10
8
3.00 0.10
(2 SIDES)
TYP
5
R = 0.05
TYP
0.70 0.05
2.55 0.05
1.15 0.05
2.00 0.10
PIN 1 BAR
TOP MARK
PIN 1
(2 SIDES)
R = 0.20 OR
0.25 × 45°
CHAMFER
(SEE NOTE 6)
PACKAGE
OUTLINE
0.56 0.05
(2 SIDES)
4
1
(DDB8) DFN 0905 REV B
0.25 0.05
0.25 0.05
0.75 0.05
0.200 REF
0.50 BSC
2.20 0.05
(2 SIDES)
0.50 BSC
2.15 0.05
(2 SIDES)
0 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
3547fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC3547
U
TYPICAL APPLICATIO
Dual 300mA Buck Converter
V
IN
2.5V TO 5.5V
C1
4.7µF
RUN2
V
RUN1
IN
L2
4.7µH
L1
4.7µH
LTC3547
SW2
SW1
V
V
OUT1
OUT2
1.8V AT 300mA
2.5V AT 300mA
C
, 10pF
C
, 10pF
R2
F2
F1
V
FB2
V
FB1
GND
R4
562k
R3
280k
R1
C
C
OUT2
OUT1
4.7µF
280k 887k
4.7µF
3547 TA02
C1, C2, C3: TAIYO YUDEN JMK316BJ475ML
L1, L2: MURATA LQH32CN4R7M33
1.8V/1.2V Dual 300mA Buck Converter
V
IN
2.5V TO 5.5V
C1
4.7µF
L2
4.7µH
L1
4.7µH
RUN2
SW2
V
RUN1
SW1
IN
V
V
OUT1
1.8V AT 300mA
OUT2
1.2V AT 300mA
LTC3547-1
V
V
FB1
FB2
C
C
OUT1
4.7µF
OUT2
GND
4.7µF
3547 TA03
C1, C
, C
: TAIYO YUDEN JMK316BJ475ML
OUT1 OUT2
L1, L2: MURATA LQH32CN4R7M33
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC3405/LTC3405A
300mA (I ), 1.5MHz, Synchronous Step-Down
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 20µA,
Q
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
DC/DC Converter
I
<1µA, ThinSOTTM Package
SD
LTC3406/LTC3406B
600mA (I ), 1.5MHz, Synchronous Step-Down
96% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 20µA,
Q
OUT
IN
DC/DC Converter
I
SD
<1µA, ThinSOT Package
LTC3407/LTC3407-2 Dual 600mA/800mA (I ), 1.5MHz/2.25MHz,
95% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 40µA,
Q
OUT
IN
Synchronous Step-Down DC/DC Converter
I
SD
<1µA, MS10E, DFN Packages
LTC3409
600mA (I ), 1.7MHz/2.6MHz, Synchronous
96% Efficiency, V : 1.6V to 5.5V, V
= 0.6V, I = 65µA,
Q
OUT
IN
Step-Down DC/DC Converter
I
SD
<1µA, DFN Package
LTC3410/LTC3410B
LTC3411
300mA (I ), 2.25MHz, Synchronous Step-Down
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 26µA, I <1µA,
Q SD
OUT
IN
DC/DC Converter
SC70 Package
1.25A (I ), 4MHz, Synchronous Step-Down
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 60µA,
Q
OUT
IN
DC/DC Converter
I
SD
<1µA, MS10, DFN Packages
LTC3531/LTC3531-3/ 200mA (I ), 1.5MHz, Synchronous Buck-Boost
95% Efficiency, V : 1.8V to 5.5V, V : 2V to 5V,
IN OUT
I = 16µA, I <1µA, ThinSOT, DFN Packages
Q SD
OUT
LTC3531-3.3
DC/DC Converter
LTC3532
500mA (I ), 2MHz, Synchronous Buck-Boost
95% Efficiency, V : 2.4V to 5.5V, V : 2.4V to 5.25V, I = 35µA,
SD
OUT
IN
OUT
Q
DC/DC Converter
I
<1µA, MS10, DFN Packages
LTC3548/LTC3548-1/ Dual 400mA and 800mA (I ), 2.25MHz,
95% Efficiency, V : 2.5V to 5.5V, V
SD
= 0.6V, I = 40µA,
Q
OUT
IN
OUT
LTC3548-2
Synchronous Step-Down DC/DC Converter
I
<1µA, MS10E, DFN Packages
ThinSOT is a trademark of Linear Technology Corporation
3547fa
LT 0906 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
© LINEAR TECHNOLOGY CORPORATION 2006
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
CB2016T2R2M8
Wire-wound Chip Power Inductors for Telecommunications Infrastructure and Industrial Equipment / Medical Devices (CB series)[CB]
TAIYO YUDEN
CB2016T330K8
Wire-wound Chip Power Inductors for Telecommunications Infrastructure and Industrial Equipment / Medical Devices (CB series)[CB]
TAIYO YUDEN
CB2016T330M
General Purpose Inductor, 33uH, 20%, 1 Element, Ferrite-Core, SMD, 0806, CHIP, 0806, ROHS COMPLIANT
TAIYO YUDEN
CB2016T330M8
Wire-wound Chip Power Inductors for Telecommunications Infrastructure and Industrial Equipment / Medical Devices (CB series)[CB]
TAIYO YUDEN
©2020 ICPDF网 联系我们和版权申明